Many types of integrated circuits are manufactured to include logic that operates at different voltage power supply levels. For example, a modern microprocessor chip may include core logic operating at a power supply voltage of 2.5 volts, which interfaces with input/output (I/O) circuitry operating in a 3.3 volt DC power supply. By way of further example, many floppy disk and hard disk controller integrated circuits interface with ISA or EISA busses that require a 5.0 volt power supply. In other instances, many PCMCIA circuit cards are manufactured to operate at 3.3 volts or 5.0 volts. Examples of prior art methods for interfacing components of mixed DC supply voltages are described in U.S. Pat. No. 5,440,244.
Devices that operate with multi-level voltage power supplies typically require a power-up sequence for proper initialization. Since the core logic may operate at a lower voltage than the periphery or I/O circuitry, it is desirable if the core voltage ramps up first. By ramping the core logic voltage supply lines prior to the I/O voltage supply lines, the inputs to the voltage level shifting circuitry associated with the core logic can initialize properly. In cases where the I/O voltage supply lines ramp up first, the level shifters may allow excessive power to be drawn by the device--possibly causing the internal CMOS circuitry to enter a latch-up condition. This problem of drawing large amounts of current upon power-up in a mixed voltage, multi-rail integrated circuit is discussed in U.S. Pat. No. 5,862,390.
Another difficulty associated with multi-power supply integrated circuits is the presence of electrostatic discharge (ESD) devices, which are included to protect the chip from destructive static discharge events. To protect against ESD events, a number of diodes are usually coupled between the various power supply lines. For example, ESD networks comprising two or more series connected diodes are typically connected to the power rail V.sub.CC to provide proper protection and noise decoupling. During power-up sequencing, the ESD diodes may transfer power from an externally supplied rail voltage to an internal rail voltage. At power-up, power may be transferred from the I/O circuitry directly to the core logic supply lines. A problem exists, however, in that the multiple number of series diodes that provide ESD protection may not allow a core operating voltage that is sufficient to properly initialize the core logic of the chip.
U.S. Pat. No. 5,625,280 teaches the use of an on-chip voltage regulator circuit to bypass ESD events in a multi-voltage environment. This solution, however, does not address the problem of how to properly initialize the various logic components of the chip that operate at different voltage power supply levels.
Although latch-up condition is one problem associated with multi-voltage integrated circuits, other problems resulting from carrier injection may also cause a reduction in reliability of the integrated circuit; particularly at power-up. To combat problems of carrier injection in a multi-voltage integrated circuit, U.S. Pat. No. 5,920,089 discloses carefully configured CMOS well and substrate structures.
Thus, a need still exists for a circuit solution to the problem of power-up in a multi-voltage integrated circuit.